Por favor, use este identificador para citar o enlazar este ítem:
http://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/1079| Reconfigurable dynamical logic gate with linear core | |
| ERIC CAMPOS CANTON ISAAC CAMPOS CANTON HARET CODRATIAN ROSU | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| H03K19/173 H03K19/1733 H03K25/04 | |
| "A dynamically reconfigurable linear core logic gate is a device that allows logical outputs dependent upon configurable parameters set within device. The device is comprised of three blocks: The first block receives at least one input signal and determines whether the signal o signals are low or high in comparison with a threshold reference signal. The second block sums the logic signals of the first block with an offset signal. The third block determines if the sum realized in the second block is a low or high by checking whether the sum falls within a predetermined interval." | |
| 2013-11 | |
| Patente | |
| Público en general | |
| CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA | |
| Aparece en las colecciones: | Patentes |
Cargar archivos:
| Fichero | Tamaño | Formato | |
|---|---|---|---|
| US8587343B2.pdf | 422.7 kB | Adobe PDF | Visualizar/Abrir |