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http://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/941| Set-reset flip-flop circuit with a simple output logic | |
| ERIC CAMPOS CANTON HARET CODRATIAN ROSU | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| https://doi.org/10.1007/s00034-011-9343-4 | |
| Set-reset flip-flop Equation of the plane Basic logic gates Bistable multivibrator | |
| "The equation of the plane (EOP) in analytic geometry is used to build a logic dynamic architecture, i.e., a combination of set-reset flip-flop (SR-FF) and basic logic gates. This is achieved by using two of the variables in the EOP as the input signals of the SR-FF and the remaining variable as the output signal. This theoretical proposal for mixing the SR-FF and the basic logic gates is confirmed experimentally by means of a simple electronic implementation." | |
| Springer Link | |
| 2012 | |
| Artículo | |
| Inglés | |
| Público en general | |
| Campos-Cantón, I., Campos-Cantón, E., Rosu, H.C. et al. Circuits Syst Signal Process (2012) 31: 753. | |
| CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA | |
| Versión revisada | |
| submittedVersion - Versión revisada | |
| Aparece en las colecciones: | Publicaciones Científicas Nanociencias y Materiales |
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| Fichero | Descripción | Tamaño | Formato | |
|---|---|---|---|---|
| CircuitsSystemsSignalProcess31(2012)753.pdf | 600.65 kB | Adobe PDF | Visualizar/Abrir |